high-speed multi-output pll clock buffe r roboclock ? cy7b9973v cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-07430 rev. *b revised september 27, 2006 features ? 10-mhz ? 200-mhz output operation ? output-to-output skews < 350 ps ? 13 lvttl 50% duty-cycle outputs capable of driving 50 terminate d lines ? phase-locked loop (pll) lock indicator ? 3.3v lvttl/lv differenti al (lvpecl) hot insertable reference inputs ? multiply/divide ratios of (4, 6, 8, 10, 12, 16, 20):(2, 4, 6, 8, 10, 12, 16, 20) ? operation with outputs operating at up to 10x input frequency ? low cycle-to-c ycle jitter (< 75 ps peak-peak) ? single 3.3v 10% supply ? pin-compatible with motorola mpc973 ? 52-pin tqfp package functional description the cy7b9973v low-voltage pll clock buffer offers user-selectable frequency control over system clock functions. this twelve output clock driver provides the system integrator selectable frequency ratios of 1:1, 2:1, 3:1, 3:2, 4:3, 5:1, 5:2, 5:3, 6:1 and 6:5 between outpu ts. an additional output is dedicated to providing feedback information to allow the internal pll to multiply an external reference frequency by 4, 6, 8, 10, 12, 16 or 20. the completely integrated pll reduces jitter and simplifies board layout. the thirteen configurable output s can each drive terminated transmission lines with impedances as low as 50 while deliv- ering minimal and specified output skews at lvttl levels. the cy7b9973v has a flexible reference input scheme with three different hot-insertion capable inputs. these inputs allow the use of either differential lvpecl or single-ended lvttl inputs which can be dynamically selected to provide the reference frequency. d q d q d q d q d q 0 1 2 4, 6, 8, 12 4, 6, 8, 10 2, 4, 6, 8 4, 6, 8, 10 data generator lock (25) qa0 (50) qa1 (48) qa2 (46) qa3 (44) qb0 (38) qb1 (36) qb2 (34) qb3 (32) qc0 (23) qc1 (21) qc2 (18) qc3 (16) qfb (29) lpf phase detector 1 0 0 1 2 2 2 2 inv_clk (14) fselfb0:1 (27,26) fselc0:1 (20,19) fselb0:1 (41,40) fsela0:1 (43,42) mr /oe (2) fselfb2 (5) ext_fb (31) tclk1 (10) tclk0 (9) tclk_sel (8) ref_sel (7) pll_en (6) pecl_clk (12) pecl_clk (11) vco_sel (52) reset vco 0 1 2 / 1 logic diagram
roboclock ? cy7b9973v document #: 38-07430 rev. *b page 2 of 8 table 1. divider function selects for qa, qb, qc fsela1 fsela0 qa fselb1 fselb0 qb fselc1 fselc0 qc 00 400 400 2 01 601 601 4 10 810 810 6 11 12 1 1 10 1 1 8 40 42 41 31 30 29 27 28 32 33 34 35 36 37 38 39 18 17 15 16 14 19 20 21 24 25 23 22 fselfb1 lock gndo qc0 vcco qc1 qc3 fselc1 vcco inv_clk qc2 fselc0 gndo fselb1 fselb0 fsela1 fsela0 qa3 vcco qa0 gndo vcco vco_sel qa1 qa2 gndo 48 49 51 50 52 47 46 45 43 44 gndo qb0 vcco qb1 gndo qb2 qfb qb3 gndo fselfb0 ext_fb vcco vccf 9 10 11 13 12 vcca pecl_clk tclk0 tclk_sel pecl_clk tclk1 ref_sel pll_en fselfb2 ft2 ft1 mr /oe gnda 8 7 6 5 4 3 2 1 cy7b9973v 26 5 2 -lea d pi nout (t op vi ew ) table 2. divider function select for qfb fselfb2 fselfb1 fselfb0 qfb 000 4 001 6 010 8 011 10 100 8 101 12 110 16 111 20 table 3. control pin function selects control pin logic ?0? logic ?1? vco_sel vco/2 vco ref_sel controlled by tclk_sel pecl tclk_sel tclk0 tclk1 pll_en bypass pll enable pll mr /oe master reset/output hi-z enable outputs inv_clk noninverted qc2, qc3 inverted qc2, qc3
roboclock ? cy7b9973v document #: 38-07430 rev. *b page 3 of 8 pin definitions name pin # type description q[a:c][0:3] qfb 50,48,46,44 38,36,34,32 23,21,18,16 29 lvttl output clock output . these outputs provide numerous divide functions determined by the fsel[a:c][0:1] and the fselfb[0:2] inputs. see table 1 and table 2 ext_fb 31 lvttl input [1] pll feedback input . this input is used to connect one of the clock outputs (usually qfb) to the feedback input of the pll. ref_sel 7 lvttl input [1] reference select input . the ref_sel input controls the reference input to the pll. when low the input is selected by the tclk_sel input. when high the pecl_clk is selected. this input has an internal pull-up. tclk_sel 8 lvttl input [1] ttl clock select input . the tclk_sel input controls which tclk[0,1] input will be used as the reference input if ref_sel is low. when tclk_sel is lo w tclk0 is selected. when tclk_sel is high tclk1 is selected. this input has an internal pull-up. tclk0 tclk1 9, 10 lvttl input [1] lvttl reference inputs . these inputs provide the reference frequency for the internal pll when selected by ref_sel and tclk_sel. pecl_clk pecl_clk 11,12 lv-diff. pecl input differential reference inputs . this lv-differential pecl input provides the reference frequency for the internal pll when selected by ref_sel. fsel[a:c][0:1] 43, 42, 41, 40, 20,19 lvttl input [1] output divider function select . each pair controls the divider function of the respective bank of outputs. see table 1 . fselfb[0:1] fselfb2 27,26 5 lvttl input [1] feedback output divider function select . these inputs control the divider function of the feedback output qfb. see table 2 . vco_sel 52 lvttl input [1] vco frequency select input . this input selects the nominal operating range of the vco used in the pll. when vco_sel is high the vco range is 200-480 mhz. when vco_sel is low the vco range is 100-240 mhz. pll_en 6 lvttl input [1] pll bypass select . when this input is high the internal phase locked loop (pll) provides the internal clocks to operate the part. wh en this input is low the internal pll is bypassed and the selected reference input provides the clocks to operate the part. ft1, ft2 3, 4 lvttl input [1] pll bypass mode control inputs . when pll_en is high these inputs are ignored and may be set to any logic level or left open. these inputs have an internal pull-up. inv_clk 14 lvttl input [1] invert mode . this input only affects the qc bank. when this input is high, qc2 and qc3 are inverted from the ?normal? phase of qc0 and qc1. when this in put is low all outputs of the qc bank are in the ?normal? phase alignment. mr /oe 2 lvttl input [1] master reset (active low) and output enable (active high) input . note: when mr /oe is deasserted (set to high) the pll will have been disturbed and the outputs will be at an indeterminate frequency until it is relocked. vcca 13 power pll power . vccf 28 power feedback buffer power . vcco 17, 22, 33, 37,45,49 power output buffer power . gnda 1 ground pll ground . gndo 15, 24, 30, 35, 39, 47, 51 ground output buffer ground . lock 25 lvttl output pll lock indicator . when high this output indicates that the internal pll is locked to the reference signal. when low the pll is at tempting to acquire lock. note: if there is no activity on the selected reference input lock may not accurately reflect the state of the internal pll. this pin will drive logic, but not thevenin terminated transmission lines. it is always active and does not go to a high impedance state. this output provides test mode information when pll_en is low. note: 1. includes internal pull-up. if this pin is left unconnected it will assume a high level.
roboclock ? cy7b9973v document #: 38-07430 rev. *b page 4 of 8 block diagram description (see figure, page 1) phase frequency detector and filter these two blocks accept signal s from the reference inputs (tclk0, tclk1 or pecl_clk) and the fb input (ext_fb). correction information is then generated to control the frequency of the voltage controlled oscillator (vco). these two blocks, along with the vco, form a (pll) that tracks the incoming reference signal. the robo973 has a flexible reference input scheme. these inputs allow the use of either di fferential lvpecl or one of two single-ended lvttl inputs. the reference inputs are tolerant to hot insertion and can be changed dynamically. vco, control logic, and divider the vco accepts analog control inputs from the pll filter block. the vco_sel control pin setting determines the nominal operational frequency range of the vco (f nom ). when vco_sel is high the vco operating range is 200?480 mhz. for systems that need lower freq uencies, vco_sel can be set low, which changes the vco operating range to 100?240 mhz. data generator the data generator is comprised of four independent banks: three banks for clock outputs and one bank for feedback. each clock output bank has four low-skew, high-fanout output buffers (q[a:c][0:3]), controlled by two divide function select inputs (fsel[a:c][0:1]). the feedback bank has one high- fanout output buffer (qfb). this output is usually connect ed to the selected feedback input (ext_fb). this feedback output has three divider function selects fselfb[0:2]. inv_clk pin function the qc bank has signal invert capability. the four outputs of the qc bank will act as two pairs of complementary outputs when the inv_clk pin is driven high. in complementary output mode, qc0 and qc1 are noninverting (i.e., in phase with the other banks), qc2 and qc3 are inverting outputs (i.e., inverted from the other banks). when the inv_clk pin is driven low, the outputs will not invert. inversion of the outputs are independent of the divide functi ons. therefore, clock outputs of qc bank can be inverted and divided at the same time. lock detect output description the lock detect output indica tes the lock condition of the integrated pll. lock detection is accomplished by comparing the phase difference between the reference and feedback inputs. an unacceptable phase error is declared when the phase difference between the two inputs is greater than about 700 ps. when in the locked state, after four or more consecutive feedback clock cycles with pha se-errors, the lock output will be forced low to indi cate out-of-lock state. when in the out-of-lock state, 32 consecutive phase-errorless feedback clock cycles are requ ired to allow the lock output to indicate lock condition (lock = high). if the feedback clock is removed after lock has gone high, a watchdog circuit is implemented to indicate the out-of-lock condition after a time-out period by deasserting lock low. this time-out period is based upon a divided down reference clock. this assumes that there is ac tivity on the selected reference input. if there is no activity on the selected reference input then the lock detect pin may not accurately reflect the state of the internal pll. the lock pin has been designed with an intentionally reduced output drive capability to minimize noise and power dissipation. this pin will drive logic, but not thevenin-termi- nated transmission lines. it is also unaffected by the mr /oe input and is always active. pll bypass mode description the device will enter pll bypass mode when the pll_en is driven low. in factory pll bypass mode, the device will operate with its internal pll disconnected; input signals supplied to the reference input will be used in place of the pll output. in pll bypass mode the ext_fb input is ignored. all functions of the device are still operational in pll bypass mode. factory test reset when in pll bypass mode (pll_en = low), the device can be reset to a deterministic state by driving the mr /oe input low. when the mr /oe input is driven low in pll bypass mode, all clock outputs will go to hi-z; after the selected reference clock pin has 5 positive transitions, all the internal finite state machines (fsm) will be set to a deterministic state. the deterministic state of the state machines will depend on the configurations of the divide selects and frequency select input. all clock outputs will stay in high-impedance mode and all fsms will stay in the deterministic state until mr /oe is deasserted. when mr /oe is deasserted (with pll_en still at low), the device will reenter pll bypass mode. safe operating zone the device will operate below its maximum allowable junction temperature (t j < 150c) in any configuration of multiply or divide with all outputs loaded to the data sheet maximum (i.e., with 25-pf load and 0-m/s air flow).
roboclock ? cy7b9973v document #: 38-07430 rev. *b page 5 of 8 absolute maximum conditions (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ............. .............. ...... ?40c to +150c ambient temperature with powe r applied .. ?40c to +125c supply voltage to ground potential ............... ?0.5v to +4.6v dc input voltage....................................?0.3v to v cc + 0.5v output current into outputs (low)............................. 40 ma static discharge voltage......... .............. .............. ...... > 2000v (per mil-std-883, method 3015) latch-up current...................................................... 200 ma operating range range ambient temperature v cc commercial 0c to +70c 3.3v 10% dc characteristics over the operating range parameter description test conditions min. typ. max. unit v ih input high voltage 2.0 ? v cc + 0.3 v v il input low voltage ? ? 0.8 v v pp peak-to-peak input voltage pecl_clk 400 ? v cc mv v cmr common mode range (crossing) pecl_clk note 2 0.8 ? v cc v v oh output high voltage all ?q? outputs i oh = ?20 ma [3] 2.4 ? ? v output high voltage lock output i oh = ?2 ma [3] 2.4 ? ? v v ol output low voltage ?q? output i ol = +20 ma ? ? 0.5 v output low voltage lock output i ol = +2 ma ? ? 0.5 v i in input current [4] all control inputs gnd < v in < v cc ??+ 150 ua pecl_clk and tclk[0:1] gnd < v in < v cc ??+ 500 ua i i hot insertion input current pecl_clk and tclk[0:1] v in < 3.63v v cc = gnd ? ? 100 ua i ccq maximum quiescent supply current sum all v cc pins pll_en=low reference off ? 50 150 ma i ccd maximum dynamic supply current (neglecting output load current) outputs unloaded fselfb = 010 ( 8) ref = 50 mhz ? 320 400 ma c in input capacitance note 5 ? ? 4 pf pll input reference characteristics over the operating range parameter description test conditions min. max. unit t r, t f tclk input rise/fall time note 5 ? 3.0 ns f ref reference input frequency 14 120 mhz t refdc reference input duty cycle 25 75 % notes: 2. v cmr is the measured at the point that both inputs achieve the same voltage. 3. the cy7b9973v clock outputs can drive series or parallel terminated 50 (or 50 to vcc/2) transmission lines on the incident edge. 4. inputs have pull-up resistors which affect input current. 5. tested initially and after any design or process changes that may affect these parameters.
roboclock ? cy7b9973v document #: 38-07430 rev. *b page 6 of 8 ac characteristics over the operating range parameter description test conditions min. typ. max. unit t r output rise time 0.8 to 2.0v note 13 0.15 ? 1.2 ns. t f output fall time 2.0 to 0.8v note 13 0.15 ? 1.2 ns. t pw output duty cycle f max < 125 mhz, notes 6, 7 t cycle /2 ?400 t cycle /2 + 200 t cycle /2 +400 ps f max > 125 mhz, notes 6, 7 t cycle /2 ?450 t cycle /2 + 225 t cycle /2 +450 ps t pd propagation delay (selected reference input rise to ext_fb rise) qfb = 8 notes 7, 8 ?350 ? +350 ps t os output to output skew notes 7, 15 ? ? + 350 ps f vco vco lock range 200 ? 480 mhz f max maximum output frequency note 12 ? ? 200 mhz t jitter (cc) cycle to cycle jitter (peak-p eak), 10,000 clocks note 16 ? + 50 + 75 ps t jitter (per) period jitter (peak-peak), 10,000 clocks note 16 ? 120 168 ps period jitter (peak-peak), rms ? 12 15.5 ps t jitter (phase) i/o phase jitter (peak- peak), 10,000 clocks, 4 feedback, vco = 250 mhz note 16 ? 175 280 ps i/o phase jitter (peak-peak), rms ? 24 46 ps t olz, t ohz output disable time note 9 1 ? 10 ns t ozl, t ozh output enable time notes 10, 11 0.5 ? 14 ns t lock maximum pll lock time ? ? 10 ms t tb total timing budget window note 14 ? ? 775 ps ac test loads and waveform [17] notes: 6. t pw is measured at vcc/2. 7. 50 transmission line terminated into v cc /2. 8. t pd is specified for a 50 mhz input reference. the t pd does not include jitter. 9. measured at 0.5v deviation from starting voltage. 10. for t ozl and t ozh minimum, c l = 0pf, r l = 1k (to v cc for t ozl , to gnd for t ozh ). for t ozl and t ozh maximum, cl= 25pf and rl = 100 (to v cc for t ozl , to gnd for t ozh ). 11. t ozl maximum is measured at 0.5v. t ozh maximum is measured at 2.4v. 12. f max measured with cl = 25pf. 13. measured with no load. 14. t tb = t pd + t os + t jitter , this parameter is calculated and is the worst case between devices. 15. all outputs operating at the same frequency. 16. not a tested parameter. guaranteed by characterization. 17. these figures are for illustrations only. the actual ate loads may vary. 2.0v 0.8v 3.3v gnd 2.0v 0.8v 3.3v output (a) lvttl ac test load <1ns <1 ns (b) ttl input test waveform r1 r2 c l r1 = 910 r2 = 910 c l <30pf (includes fixture and probe capacitance) r1 = 100 r2 = 100 c l < 25 pf (at output pin) for lock output only for all other outputs 90% 10% 2.0v 1.0v 90% 10% <1ns <1ns (c) lvpecl input test waveform
roboclock ? cy7b9973v document #: 38-07430 rev. *b page 7 of 8 ? cypress semiconductor corporation, 2003. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. roboclock is a registered trademark of cypress semiconductor. all product and company names mentioned in this document are the trademarks of their respective holders. ac timing diagrams ordering information ordering code package name package type operating range cy7b9973v-ac a52 52-lead thin quad flat pack commercial package diagrams tclk[0:1] ext_fb qa[0:3] t pd t jitter or pecl_clk qb[0:3] qc[0,3] qfb qa[0:3] t os qb[0:3] qc[0,3] qfb qa[0:3] qb[0:3] qc[0,3] qfb other any t os t pw t pw t refdc t refdc v cc 2 52-lead thin plastic quad flat pack (10 10 1.4 mm) a52 51-85131-**
roboclock ? cy7b9973v document #: 38-07430 rev. *b page 8 of 8 document history page document title: cy7b9973v roboclock ? high-speed multi-output pll clock buffer document number: 38-07430 rev. ecn no. issue date orig. of change description of change ** 115842 06/10/02 hwt new data sheet *a 128182 09/15/03 rgl added phase and period jitter specifications tightened duty cycle spec and split duty cycle based on output frequency *b 506217 see ecn rgl minor change: to post on web
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